The present invention relates to a frequency and phase detection circuit in an NRZ bit synchronous system responsive to NRZ data and outputs from a voltage controlled oscillator (herein-after referred to as VCO) for regenerating a bit synchronous clock from the NRZ data.
In the prior art, a system suitable to retiming the phase of the generated clock after nonlinearly processing and filtering the inputted NRZ data for extracting a clock component driving the inputted NRZ data from the frequency spectrum of the inputted data was used.
Recently, in the bit synchronization system using PLL (Phase Locked Loop), the advanced frequency and phase detection circuit which can generate the transition clock in centre of the eve pattern of NRZ data, has been devised by Mr. Charles R. Hogge in U.S. Pat. No. 4,535,459. However, in this circuit devised by Mr. Hogge a difference in the phase of two output waveforms from the frequency and phase detection circuit always is present if the circuit does not include a delay element for delaying the clock by a half-period time interval of the clock driving the NRZ data such that a jitter component can occur in the VCO clock.
When using the delaying element in conjunction with the Hogge circuit, the upper limit frequency and the lower limit frequency in a fixed range may become asymmetrical since it is difficult to delay the clock exactly by a half-period because of the technical limit to the delaying element. A resulting disadvantage is that substantial capture range of PLL circuit is narrowed.